(1) Field of the Invention
The invention relates to a method of fabricating semiconductor memory devices employing floating gates, and more particularly, to a method of improving coupling ratios of semiconductor memory devices employing floating gates.
(2) Description of the Prior Art
One class of semiconductor memory devices employ floating gates; that is, gates which are completely surrounded by an insulating layer, such as a silicon oxide. The presence or absence of charge in the floating gates represents binary information. These are called electrically programmable read only memories (EPROM). EEPROMS are erasable electrically programmable read only memories. "Flash" memory devices are those in which all of the cells can be erased in a single operation.
A typical Flash EEPROM of the prior art is illustrated in FIG. 1. A thin tunnel oxide layer 12 is formed on the surface of a semiconductor substrate 10. The tunnel oxide is necessary for the erasing function of the cell. The memory cell consists of the floating gate 14, interpoly dielectric layer 16, and the control gate 18. Source and drain regions 20 are shown on either side of the gate structure. Several problems exist with the prior art memory cell. The coupling ratio of the cell is low because of the thin tunnel oxide which exists over the entire channel area. As the size of the cell shrinks to the sub-micron regime, it suffers from short channel effect. That is, the transistor's threshold voltage and drain to source punchthrough voltage are reduced.
U.S. Pat. Nos. 5,180,680 to M. T. Yang and 5,049,515 to Tzeng show EEPROMs using a trench process.